An image is a visual representation of something that has been created or copied and stored in electronic form. Securing images is becoming an important concern in today’s information security due to the extensive use of images that are either transmitted over a network or stored on disks. Since public media are unreliable and vulnerable to attacks, Image encryption is the most effective way to fulfil confidentiality and protect the privacy of images over an unreliable public media.In this paper a new image encryption algorithm based on Advanced Encryption Standard and DNA sequence is proposed. We present how to encode and decode data in a DNA sequence based on Codon replacement and how to perform the different steps of AES based DNA. The algorithm is implemented in MATLAB 2012b and various performance metrics are used to evaluate its efficacy. The theoretical and experimental analysis show that the proposed algorithm is efficient in speed and precision. Furthermore, the security analysis proves that proposed algorithm has a good resistance against the noise and known attacks; So that Unbreakability of proposed algorithm is 37.48% better than the compared algorithms.

This paper mainly focused on implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. This method can make it a very low-complex architecture, especially in saving the hardware resource in implementing the AES InverseSub Bytes module and Inverse Mix columns module. As the S -box is implemented by look-up-table in this design, the chip area and power can still be optimized. The new Mix Column transformation improves the performance of the inverse cipher and also reduces the complexity of the system that supports the inverse cipher. As a result this transformation has relatively low relevant diffusion power. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.

Side-channel attacks are considered to be the most important problems of modern digital security systems. Today, Differential Power Attack (DPA) is one of the most powerful tools for attacking hardware encryption algorithms in order to discover the correct key of the system. In this work, a new scheme based on randomizing power consumption of a fixed-operation logic gate is proposed. The goal of this method is enhancing the immunity of AES algorithm against DPA. Having a novel topology to randomize the power consumption of each Exclusive-NOR gate, the proposed circuit causes random changes in the overall power consumption of the steps of the algorithm; thus, the correlation between the instantaneous power consumption and the correct key is decreased and the immunity of the AES implementations which the key is injected into their process through Exclusive-NOR gates is extremely increased. The proposed method can be used as a general hardening method in the majority of cryptographic algorithms. The results of theoretical analysis and simulations in 90-nm technology demonstrate the capability of the proposed circuits to strengthen AES against DPA. The CMOS area and power consumption overhead is less than 1%.

This paper introduces a high-Speed fault-resistant hardware implementation for the S-box of AES cryptographic algorithm, called HFS-box. A deep pipelining for S-box at the gate level is proposed. In addition, in HFS-box a new Dual Modular Redundancy based (DMR-based) countermeasure is exploited for fault correction purpose. The newly introduced countermeasure is a fault correction scheme based on DMR technique (FC-DMR) combined with a version of the time redundancy technique. In the proposed architecture, when a transient random or malicious fault(s) is detected in each pipeline stage, the error signal corresponding to that stage becomes high. The control unit holds the previous correct value in the output of our proposed DMR voter in the other pipeline stages as soon as it observes the value ‘1’ on the error signal. The previous correct outputs will be kept until the fault effect disappears. The presented low-cost HFS-box provide a high capability of fault resistance against transient faults with any duration by imposing low area overhead compared with similar fault correction strategies, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original S-box implementation.

Fault attack techniques are powerful and efficient cryptanalysis methods to find the secret key of cryptographic devices. Thus, several methods have been introduced to offset this type of side channel attack. On the other hand, some techniques were presented to locate and detect faults in the implementations of symmetric and asymmetric encryption/decryption algorithms. To our best knowledge, this paper is the first article which examines the effectiveness of fault tolerance techniques to prevent fault attacks. Also, we introduce a minimum time redundant method of using the inverse modules for Concurrent Error Detection (CED). The usage of Error Correction Codes (ECe) in implementations of Advanced Encryption Standard (AES) is another approach that is proposed in this article. We present the comparison between the usage of the proposed ECCs to make fault tolerant implementation and to resist against fault attacks. Experimental results of one of the proposed ECCs show that almost all possible faults are detected, while some of them are corrected. Thus, it resists against approximately all injected faults to attack on the implementation of AES algorithm.

This paper describes the implementation of a low power and high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES (Advanced Encryption Standard), in order to decrease the power using retiming and glitch and operand isolation techniques in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Such procedure makes AES suitable for fast image encryption.Implementation of a 128-bit AES on FPGA of Altera Company has been done, and the results are as follows: throughput, 6.5 Gbps in 441.5 MHz and 130mw power consumption. The time of encrypting in tested image with 32*32 sizes is 1.25ms.

In our days, the need for secure protocols and devices seems to be one of the most important issues in the communication systems. Template attacks is a powerful kind of simple power analysis attack that is able to effectively identify and retrieve efficiently the instructions executed by a typical processor and the Hamming weight of their operands. It is usually carried out by using templates that are created from the samples of power consumed by the device on a test platform and statistical analysis of real measurements. This paper describes practical implementation of this attack against the realization of the Advanced Encryption Standard (AES) on ARM-LPC processor. In order to mount the attack, the power samples of the cryptoprocessor processor during the execution of the AES was recorded and exported to the feature extraction and reduction algorithm. Then, the reduced samples were categorized using the machine learning algorithm. Due to more complex architecture, lower power consumption and larger number of pipeline stages compared to other microprocessors which make the attack more difficult, practical implementation of this attack on ARM processor has received less attention in related articles. The main contribution of this paper is efficient use of machine intelligence in improving the attack performance such that the improved attack is able to recover the Hamming weight of the output of the first AES SBox with 77% success rate and correct identification of the instructions of the processor with 55% success rate in average.

With the development of the electronic industry and the advent of modern processors, the attack model in the algorithms and encryption protocols also changed. In spite of computational complexity in algorithms and cryptographic protocols, implementations can be a factor for the leakage of confidential information. The attacker can attack when electronic components are executing the encryption operators using the secret key on sensitive data. As a result of computing, there is a leak of information in electronic components where attacks are called side-channel attacks. one of the most important sources of information leakage of side channels is time changes due to the execution of computation. The accesses to memory and the presence of branches in the program are expensive at runtime, so the processors use cache memory and branch-prediction to reduce this cost. Unfortunately, this optimization during execution leads to time changes in the execution of a program. The cache in the time side-channel attacks is more challenging and more practical. In this paper, we will review a variety of memory attacks on the implementation of the AES cipher algorithm. by implementing the attacks and comparing the results, we will extract and compare the security weaknesses of implementing the AES cipher algorithm against cache attacks.

Advanced Encryption Standard (AES) is one of the most common standard encryption algorithms. Inspired by its characteristics, AES algorithm can be implemented on various hardware platforms such as FPGA. Also, the data path can be implemented in either loop-unrolling or rolling architecture. These two architectures have direct impact on the amount of area consumption on the chip as well as system throughput. Then, a smart design should be able to consider the trade-off between area and throughput and provide a good balance between these two conflicting factors. In this paper, we propose such a design to represent the area-throughput trade-off for FPGA implementation of the AES algorithm. With loop unrolling and pipelining techniques, throughput of 71.35 Gbps is achievable in Virtex 7 FPGA (xc7v585t-3ff1157). This design has just used 3669 Slices on the chip. The extracted results from the Place & Route report of Xilinx ISE 14.2 indicates that the maximum attainable clock frequency is 570.776 MHz.